SPI4 sink payload dip4 error

This article describes the log message reported when an S2H/H2S FPGA detects a parity error on packet data:

SPI4.2 is the OIF’s System Packet Interface Level 4 (SPI-4) Phase 2 standard.

S2H/H2S FPGA is a bridge between the HSL2 and the SPI-4.2 interface; it converts SPI-encoded data to HSL2 data, or vice versa.
DIP is Diagonal Interleaved Parity. DIP-4 implies 4-bit parity.
Several field-replaceable units (FRUs) — for example, MX-DPC and MPCs, M120-RFPC, and 10XGE Type4 PIC (Quervo) — have an S2H/H2S FPGA block.
In SPI, the sink core is an RX block, while the source core is a TX block.

Syslog:

SPI4 sink error types

SPI4 source error types

A temporary data corruption owing to a hardware transition (FPC or PIC reset) or corrupted traffic.

If this message is reported in the Syslog after the hardware transition is completed, there could be a problem with the hardware.

Reboot or replace the PIC.

If the error continues to be reported in the Syslog, reboot the PIC (if possible) so the software can check the hardware step-by-step during reinitialization.

If the software fails to initialize the PIC due to a hardware error, the message below is reported in the Syslog:

If rebooting doesn’t solve the problem, replace the PIC.

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