High CPU occurs in all FPC when datapath debug is enabled

On an SRX1K/3K, despite CPU in both SPU and RE is low, High CPU in ‘show chassis fpc’ is observed when datapath debug is enabled.

On an SRX1K/3K device, low CPU is seen in both SPU and RE. However, when datapath debug is enabled, the CPU in ‘show chassis fpc’ is high.
In the following example, 100% CPU is seen in all FPC:
Note: Slot 7 and 8 is SPC

RE and SPU CPU is very low:

Less than 6K concurrent sessions in SRX:

Based on the vty output of CPP0 below, high CPU in CPP is mostly due to the thread bcmCNTR.X, which is a period thread to scan the counters and state of the BCM Chip. Whenever datapath debug is enabled, CPU in CPP is used by this thread to collect counter for datapath debug output.

bcmCNTR.X use up CPU from “show thread” in node0.cpp0:

Note that CPP is the control CPU monitoring status of SPC/IOC/NPC in SRX1K/3K. The command, ‘show chassis fpc’ displays CPU usage of CPP, whereas ‘show security monitoring performance spu’ displays the CPU usage of SPU which processes network traffic. Hence, high CPU in CPP (show chassis fpc) should not impact traffic.

It is expected for the CPU in CPP to be as high as 100%. Also, this thread’s priority is medium. When the system has the higher priority threads, it will give out the CPU time to other higher priority threads. Hence, despite CPU in CPP is 100%, it does not affect the whole system or network traffic (which is handled by SPU).

Note: In SRX5K, there is individual control CPU on each SPC/IOC card. Therefore, ‘show chassis fpc’ may display different CPU usage for different cards. But for SRX1K/SRX3K, there is only one control CPU in CPP for all SPC/NPC/IOC cards. The CPU usage should be from one single value and it should be same.

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James Palmer

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